1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly, a method which simplifies the processes by which a CMOS (complementary) metal-oxide semiconductor) unit for an ordinary logic circuit and a CMOS unit of a high dielectric strength are manufactured in the same substrate.
2. Description of the Prior Art and Problems Therewith
The high integration of a high voltage semiconductor device has been advancing along with the progress of semiconductor technology. Large-scale integrated circuits, in which a CMOS unit for an ordinary logic circuit and a CMOS unit are provided together in the same substrate, have recently been developed.
When the field-effect transistor (FET) of a high voltage CMOS unit is to be manufactured, the construction of the unit and the method of manufacturing the unit are determined upon consideration of the following problems:
(1) punch-through phenomenon between the source and the drain, in which a depletion layer extends to the source region if the length of the channel is small;
(2) dielectric breakdown between the gate and the drain; and
(3) avalanche caused by the concentration of an electric field near the surface of the drain region which occurs when the drain region and the gate are overlaid with an interposed thin insulator film.
In order to solve the above-mentioned problems, the procedures described below have been adopted:
(1) with respect to the punch-through phenomenon, the gate is provided in common thereto to increase the channel length;
(2) with respect to the dielectric breakdown, the thickness of the insulator film (as shown at 111 in FIG. 3(a)) at the place of the dielectric breakdown is increased or the distance between the gate (as shown in 112 FIG. 3(a)) and the drain (as shown at 113 in FIG. 3(a)) is sufficiently large so as to weaken the electric field between the gate and the drain; and
(3) with respect to the avalanche, an offset gate structure is provided to weaken the electric field, or an insulator film is provided on the structure to make a stacked gate (as shown in 112a in FIG. 3(b)) to control the electric field.
In another procedure, an impurity is diffused at a low concentration to provide a low-concentration layer (as shown at 113a in FIG. 3(c)) of the same type as the drain region (as shown at 113 in FIG. 3(c)) to provide a channel region as an offset region. A field plate (as shown at 115 in FIG. 3(c)) is provided by extending the drain (as shown at 123 in FIG. 3(c)) toward the source, to reduce the concentration of the electric field at the conjoined end of the drain. However, if the field plate is extended as the thickness of the gate insulator film remains fixed, high voltage is likely to act on the film to cause electrostatic breakdown. On the other hand, if the thickness of the gate insulator film is increased, the original effect of the field plate, to reduce the concentration of the electric field at the conjoined end, is diminished. For that reason, there is a limit to the effectiveness of improving the dielectric strength by modifying the field plate.
Still another procedure has been considered effective in which a low-concentration impurity layer is provided around a high-concentration impurity region as a source-drain region and a field plate is provided to reduce the concentration of the electric field at the conjoined end to improve the dielectric strength. However, this construction is complicated, and diffusion must be performed two times.
When such a construction is adopted for a high voltage MOSFET (metal-oxide semiconductor field-effect transistor), particularly, when the high voltage CMOS unit and the CMOS unit for an ordinary logic circuit are integrated in a single substrate, a large number of processes are needed.
For example, when a p-type well is made in an n-type silicon substrate to provide a high voltage CMOS unit and a CMOS unit for an ordinary logic operation, a p.sup.- -type high voltage layer is used as the offset low-resistance layer of a p-type MOSFET. On the other hand, another p.sup.- -type layer is used as the channel stopper of an n-type MOSFET for an ordinary logic operation, which is provided in the p-type well.
An n.sup.- -type layer is used as the offset low-resistance layer of a high-voltage n-type MOSFET manufactured in the p-type well, while another n.sup.- -type layer is used as the channel stopper of a p-type MOSFET for an ordinary logic operation, which is manufactured in the n-type silicon substrate.
It will be understood from the above description that there are many section, in each of which a CMOS unit for an ordinary logic operation and a high voltage CMOS unit have the same construction although they perform different functions, as shown in TABLE I below.
TABLE I __________________________________________________________________________ Device Function High-Voltage Construction Ordinary logic CMOS CMOS __________________________________________________________________________ N.sup.- -type injection (1) Only used as channel (1) Used as channel stopper layer stopper under ring gate provided P.sup.- -layer around (2) Used as offset low-resistance layer LOCOS (1) Used as element (1) Used as element Insulator film separation film separation film (2) Used as thick insulator film between gate and drain High concentration (1) Formation of source (1) Formation of source and n.sup.+ -type and drain layers p.sup.+ -type injection (Formation of low- layers based on self- concentration n.sup.- -type and alignment of gate p.sup.- -type injection layers of large diffusion coefficient and same conduction type) Aluminum electrode (1) Used as source and (1) Used as source and drain electrodes electrodes (2) Used as field plate __________________________________________________________________________
In the above-described conventional procedures, the various regions are made separately. For this reason, the processes for manufacturing these units are complicated and large amounts of time are required to perform the manufacturing processes.
The present invention was made in consideration of the above-described circumstances. Accordingly, it is an object of the present invention to simplify the processes for manufacturing a high voltage semiconductor device which includes both a MOS unit and a CMOS unit for an ordinary logic operation.